Search results for "Semiconductor memory"
showing 5 items of 5 documents
A Low Cost Solution for 2D Memory Access
2006
Many of the new coding tools in the H.264/AVC video coding standard are based on 2D processing resulting in row-wise and column-wise memory accesses starting from arbitrary memory locations. This paper proposes a low cost solution for efficient realization of these 2D block memory accesses on sub-word parallel processors. It is based on the use of simple register-based data permutation networks placed between the processor and memory. The data rearrangement capabilities of the networks can further be extended with more complex control schemes. With the proposed control schemes, the networks enable row and column accesses from arbitrary memory locations for blocks of data while maintaining f…
Analyzing the Energy Efficiency of the Memory Subsystem in Multicore Processors
2014
In this paper we analyze the energy overhead incurred when operating with data stored in different levels of the memory subsystem (cache levels and DDR chips) of current multicore architectures. Our approach builds upon servet, a portable framework for the memory characterization of multicore processors, extending this suite with a power-related test that, when applied to a platform equipped with a power measurement mechanism, provides information on the efficiency of memory energy usage. As additional contributions, i) we provide a complete experimental study of the impact that the CPU performance states (also known as P-states) exert on the memory energy efficiency of a collection of rece…
A block access unit for 2D memory access
2007
Many of the coding tools in the H.264/AVC video coding standard are based on 2D processing resulting in rowwise and column-wise memory accesses starting from arbitrary memory addresses. This paper discusses a low-cost hardware realization of these accesses on sub-word parallel processors. The proposed block access unit is placed between the processor and memory. It supports unaligned 2D block accesses according to several 2D access patterns. The 2D block accesses are pipelinable and they result in minimum number of memory accesses required to deliver the desired data.
Location of holes in silicon-rich oxide as memory states
2002
The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh …
Compositional and Optical Gradient in Films of PbZrxTi1-xO3 (PZT) Family
2011
Pb(ZrxTi1-x)O3 (PZT) (x = 0-1) films have attracted the attention of researchers for the past 30 years due to their excellent ferroelectric (FE) and electromechanical properties, which have led to the commercialization of thin PZT films for ferroelectric random access memory (FeRAM), forming a market of several millions USD annually. Ferroelectricity of perovskite oxide thin films, especially PZT thin films, can be exploited in semiconductor devices to achieve non-volatile random access memory (NVRAM) with high-speed access and long endurance, which can overcome the barriers, encountered in current semiconductor memory technologies. The ferroelectricity can be also exploited to voltage depe…